A wide-bandgap semiconductor has attracted a lot of attention as a semiconductor material that could be potentially used to make a semiconductor device that has a high breakdown voltage and that can make a huge amount of current flow through it (i.e., a so-called “power device”). Among other things, silicon carbide (SiC) has a much higher dielectric breakdown voltage than any other wide-bandgap semiconductor, and therefore, is expected to be the best semiconductor material to make a next-generation low-loss power device. As a quality silicon dioxide (SiO2) film can be formed on SiC by thermal oxidation, an insulated gate SiC power MISFET (metal-insulator-semiconductor field effect transistor) that uses such a silicon dioxide film as its gate insulating film is currently under development.
However, as such a SiC-MOS structure has a very high density of interfacial levels at the SiO2/SiC interface, its channel mobility is low, its channel resistance will be high when it is implemented as a SiC power MISFET, and therefore, the low loss property that SiC has by nature cannot be make full use of, which is a problem.
Thus, to overcome such a problem, Patent Document No. 1 discloses a vertical SiC power MISFET with the structure shown in FIG. 9. As shown in FIG. 9, the SiC power MISFET includes a SiC semiconductor substrate 2 and an n-type drift layer 3, which is arranged on the SiC substrate 2. A p-body region 4a has been defined in the drift layer 3. Inside the body region 4a, further defined are an n-type source region 5 and a p-type contact region 4b. An n-type doped region 27 is defined in a surface region so as to extend from the source region 5 through the body region 4a and also extend from the body region 4a through the drift layer 3. The source region 5 and the contact region 4b make ohmic contact with an ohmic electrode 6 arranged on the surface of the drift layer 3.
In the FET illustrated in FIG. 9, the channel is defined as the region between the two n-type doped regions 27. By adopting such a structure, a channel length of 1 μm or less can be achieved. As a result, even if the channel mobility is low due to a high density of those interfacial levels, the channel resistance can still be reduced.
On the other hand, the gate insulating film of a SiC power MISFET should have sufficiently high reliability in OFF state. When a high voltage is applied to the drain electrode of a SiC power MISFET in OFF state, a high electric field is applied to a portion of the gate insulating film that is located over the gap between the body regions. Particularly, an electric field with the maximum intensity is applied to a portion of the gate insulating film that is located at the intermediate point R over the gap between the body regions 4a shown in FIG. 9. That is why the intensity of the electric field to apply should be determined so as not to cause a breakdown in the gate insulating film at the point R. This is because if a breakdown happened in the gate insulating film, the power circuit would be affected seriously.
Thus, to overcome such a problem, Patent Document No. 2 discloses a technique for reducing the channel resistance by providing an accumulated channel (i.e., an n-type channel region 28) in an upper portion of each p-type body region 4a as shown in FIG. 10. According to Patent Document No. 2, by providing no n-type heavily doped region in a surface region of the drift layer 3 between the body regions 4a, it is possible to prevent the intensity of the electric field from being excessively high at the point R.